DDR2控制器，时序约束时出错，有哪位大神帮帮忙？
时间：10-02
整理：3721RD
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PhysDesignRules:2449 - The computed value for the VCO operating frequency of PLL_ADV instance
my_mig_inst/memc3_infrastructure_inst/u_pll_adv is calculated to be 119.999998 MHz. This falls below the operating
range of the PLL VCO frequency for this device of 400.000000 - 1080.000000 MHz. Please adjust either the input
frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT or the division factor divCLK_divIDE, in order to
achieve a VCO frequency within the rated operating range for this device.
时序约束时出现以上问题，该怎么办?
my_mig_inst/memc3_infrastructure_inst/u_pll_adv is calculated to be 119.999998 MHz. This falls below the operating
range of the PLL VCO frequency for this device of 400.000000 - 1080.000000 MHz. Please adjust either the input
frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT or the division factor divCLK_divIDE, in order to
achieve a VCO frequency within the rated operating range for this device.
时序约束时出现以上问题，该怎么办?
PLL的工作范围不合法?
英文不是写的很清楚吗?
得怎么修改?对pll不是很熟悉，谢谢
有困难先查手册
几个要素先确认清楚
1、PLL要求的输入的参考钟合理频点范围
2、PLL输出时钟频点范围
3、分频、倍频系数配置的原理
4、逻辑需要的时钟频点是多少
5、PLL能不能配出这个频点
按上面的告警
VCO的频点要配置在400M以上
然后通过修改div分频系数达到你要用的输出频率
频率换算关系自己去看PLL的手册
我靠 不是自动生成么 还要手动改配置PLL，有点幽默啊，从来都是生成IP核的时候都配好了