quartus用IP核生成DDR3 SDRAM CONTROLLER WITH UNIPHY时编译出错
时间：10-02
整理：3721RD
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最近项目要求调试DDR3，所以打算用altera的IP核DDR3 SDRAM CONTROLLER WITH UNIPHY生成的例子工程（example project)进行调试，配置好参数后，生成IP核，但在编译的时候出现如下错误：
Error (129037): Output port OUTCLK on atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy", which is a stratixv_phy_clkbuf primitive, is driving one or more illegal destinations。
Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_write_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal
Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_mem_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal
Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_c2p_write_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal
有了解的大神吗。芯片使用的是STRATIX V，型号5SGSMD6K2F40C2L，DDR是hynix 的 1600 2GB内存，参数配置严格按照内存DATASHEET。
Error (129037): Output port OUTCLK on atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy", which is a stratixv_phy_clkbuf primitive, is driving one or more illegal destinations。
Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_write_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal
Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_mem_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal
Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_c2p_write_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal
有了解的大神吗。芯片使用的是STRATIX V，型号5SGSMD6K2F40C2L，DDR是hynix 的 1600 2GB内存，参数配置严格按照内存DATASHEET。
在线等
怀疑你的控制器的参考时钟输入和控制器管脚不在器件的一个side
我都没有分配管脚，分析综合的时候就报错了
我发现如果使用DDR例子工程的话，生成IP核那个工程是不需要编译的，只需要编译在生成IP核时产生的那个例子工程就行了
问题解决了 吗?怎么解决的?
问题解决了，首先例化的时候不能接后面几个PLL输出断口，然后编译第一步，再然后运行一次pin assignment脚本文件，然后全编译即可
多谢啦
I learn it, Thank you