VHDL仿真component 和 entity存在端口不匹配

如题，请各位大神指导
在Modelsim中仿真是正确的，也出了波形图
在Actel Libero中check hdl file无错，也可以进行综合，但启动Modelsim显示如下错误
** Failure: (vsim-3807) Types do not match between component and entity for port "num"
检查程序发现两者其实是完全对应的
请问这个问题如何解决

程序：
-- edges_counter.vhd
----------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.numeric_std.ALL;
----------------------
ENTITY edges_counter IS
  PORT(clk:IN STD_LOGIC;
       num:BUFFER NATURAL RANGE 0 TO 100000
      );
END edges_counter;
----------------------
ARCHITECTURE edges_counter OF edges_counter IS
SIGNAL a:NATURAL RANGE 0 TO 100000;
SIGNAL b:NATURAL RANGE 0 TO 100000;
BEGIN

PROCESS(clk)
   VARIABLE temp1 : NATURAL RANGE 0 TO 100000;
   BEGIN
    IF(clk'EVENT AND clk='1')THEN
      temp1 := temp1+1;
      a<=temp1;
    END IF;
  END PROCESS;
PROCESS(clk)
   VARIABLE temp2 : NATURAL RANGE 0 TO 100000;
   BEGIN
    IF(clk'EVENT AND clk='0')THEN
      temp2 := temp2+1;
      b<=temp2;
    END IF;
  END PROCESS;
  num<=a+b;
END edges_counter;
---------------------------
-- testbench.vhd
---------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.numeric_std.ALL;
---------------------
ENTITY testbench IS
END testbench;
---------------------
ARCHITECTURE testbench OF testbench IS
  COMPONENT edges_counter IS
      PORT(clk:IN STD_LOGIC;
           num:BUFFER NATURAL RANGE 0 TO 100000
          );
  END COMPONENT edges_counter;
  SIGNAL clk:STD_LOGIC;
  SIGNAL num:NATURAL RANGE 0 TO 100000;
  BEGIN
  SIMINSTANCE:edges_counter PORT MAP(clk,num);
  clk_generationROCESS
                   BEGIN
                   clk<='1';
                   wait for 20 ns;
                   clk<='0';
                   wait for 20 ns;
                 END PROCESS clk_generation;
END testbench;  
----------------------