Some questions about the market！
时间：10-02
整理：3721RD
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Hi,
I'm an ENGINEER starting in the ASIC world. Can you answer some Questions? The e Verification Language is used today? I heard about SystemVerilog and SystemC but Not so much about e from Cadence. Specman Elite of belongs to which Software Suite from cadence? INCISIV? IUS? What Hardware Verification Language that is worth investing my time? Thanks for your Attention！
I'm an ENGINEER starting in the ASIC world. Can you answer some Questions? The e Verification Language is used today? I heard about SystemVerilog and SystemC but Not so much about e from Cadence. Specman Elite of belongs to which Software Suite from cadence? INCISIV? IUS? What Hardware Verification Language that is worth investing my time? Thanks for your Attention！
Still,
What other forums do you suggest for ASIC / FPGA? (EETOP is amazing！)
For hardware verification, it seems that the industry will settle on SystemVerilog. Partly due to that it is open and low cost.
If you have time, learning C++/SystemC will be time well spent for your understanding of some SystemVerilog concepts. And System C is still used widely in system modeling.
e/Specman is still great in its verification methodology, SystemVerilog/UVM borrows a lot from it. But its license fee is way too high.