求大神把下面这段代码转成VHDL

module ADDRESS(
clk_50M,
clk_25M,
rst,
ad_address,
pci_address
);
input clk_50M;
input clk_25M;
input rst;
output [8:0]ad_address;
output [7:0]pci_address;
reg [8:0]ad_address_r;
reg[7:0]pci_address_r;
assign ad_address=ad_address_r;
assign pci_address=pci_address_r;
always@(posedge clk_50M or posedge rst)
begin
if(rst)
begin
ad_address_r<=9'd5;
end
else if(ad_address_r==9'd511)
begin
ad_address_r<=9'd0;
end
else
begin
ad_address_r<=ad_address_r+9'd1;
end
end
always@(posedge clk_25M or posedge rst)
begin
if(rst)
begin
pci_address_r<=8'd0;
end
else if(pci_address_r==8'd255)
begin
pci_address_r<=8'd0;
end
else
begin
pci_address_r<=pci_address_r+8'd1;
end
end
endmodule