ise 时序仿真问题
代码贴出来看看。说不定是仿真语言的问题
这是计数器的程序：library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity jishuqi is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
counter : out STD_LOGIC_VECTOR (2 downto 0));
end jishuqi;
architecture Behavioral of jishuqi is
signal b:std_logic_vector(2 downto 0);
begin
counter<=b;
process(clr,clk)
begin
if clr='0' then
b<="000";
else
if(clk'event and clk='1')then
b<=b + 1;
end if;
end if;
end process;
end Behavioral;
这是译码器的程序：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity yimaqi is
Port ( clr : in STD_LOGIC;
counter : in STD_LOGIC_VECTOR (2 downto 0);
qout : out STD_LOGIC_VECTOR (7 downto 0));
end yimaqi;
architecture Behavioral of yimaqi is
signal i:integer;
begin
i<=conv_integer(counter);
process(clr,i)
begin
if clr='0' then
qout<="11111111";
else
qout<="11111111";
qout(i)<='0';
end if;
end process;
end Behavioral;
这是顶层的程序：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
qout : out STD_LOGIC_VECTOR (7 downto 0);
pout : out STD_LOGIC_VECTOR (2 downto 0));
end top;
architecture Behavioral of top is
signal a:std_logic_vector(2 downto 0);
COMPONENT jishuqi
PORT(
clk : IN std_logic;
clr : IN std_logic;
counter : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
COMPONENT yimaqi
PORT(
clr : IN std_logic;
counter : IN std_logic_vector(2 downto 0);
qout : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
pout<=a;
Inst_jishuqi: jishuqi PORT MAP(
clk =>clk ,
clr =>clr ,
counter => a
);
Inst_yimaqi: yimaqi PORT MAP(
clr =>clr ,
counter => a,
qout => qout
);
end Behavioral;
这是约束的程序：
NET "qout[7]" IOSTANDARD = LVCMOS33;
NET "qout[6]" IOSTANDARD = LVCMOS33;
NET "qout[5]" IOSTANDARD = LVCMOS33;
NET "qout[4]" IOSTANDARD = LVCMOS33;
NET "qout[3]" IOSTANDARD = LVCMOS33;
NET "qout[2]" IOSTANDARD = LVCMOS33;
NET "qout[1]" IOSTANDARD = LVCMOS33;
NET "qout[0]" IOSTANDARD = LVCMOS33;
NET "clk" IOSTANDARD = LVCMOS33;
NET "clr" IOSTANDARD = LVCMOS33;
NET "qout[4]" LOC = N8;
NET "qout[2]" LOC = U7;
NET "qout[0]" LOC = U8;
NET "qout[5]" LOC = M8;
INST "clk_BUFGP" LOC = V10;
NET "clk" LOC = V10;
NET "clr" LOC = U10;
NET "qout[7]" LOC = T7;
NET "qout[6]" LOC = V7;
NET "qout[3]" LOC = V6;
NET "qout[1]" LOC = P8;
#Created by Constraints Editor (xc6slx16-csg324-3) - 2014/03/08
NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50 %;
INST "qout[0]" TNM = "group";
INST "qout[1]" TNM = "group";
INST "qout[2]" TNM = "group";
INST "qout[3]" TNM = "group";
INST "qout[4]" TNM = "group";
INST "qout[5]" TNM = "group";
INST "qout[6]" TNM = "group";
INST "qout[7]" TNM = "group";
#Created by Constraints Editor (xc6slx16-csg324-3) - 2014/03/08
TIMEGRP "group" OFFSET = OUT 20 ns AFTER "clk";
NET "pout[2]" LOC = F17;
NET "pout[1]" LOC = K12;
NET "pout[0]" LOC = E16;
NET "pout[2]" IOSTANDARD = LVCMOS33;
NET "pout[1]" IOSTANDARD = LVCMOS33;
NET "pout[0]" IOSTANDARD = LVCMOS33;
#Created by Constraints Editor (xc6slx16-csg324-3) - 2014/03/08
INST "pout<0>" TNM = tuan;
INST "pout<1>" TNM = tuan;
INST "pout<2>" TNM = tuan;
TIMEGRP "tuan" OFFSET = OUT 20 ns AFTER "clk";
这是计数器的测试程序：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY jishuqitest IS
END jishuqitest;
ARCHITECTURE behavior OF jishuqitest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT jishuqi
PORT(
clk : IN std_logic;
clr : IN std_logic;
counter : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal clr : std_logic := '0';
--Outputs
signal qout : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: jishuqi PORT MAP (
clk => clk,
clr => clr,
counter => qout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
clr<='0';
wait for 100 ns;
clr<='1';
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
如果是功能仿真没问题而时序仿真有问题，我个人怀疑是不是你加的激励的复位信号的问题，你的复位信号撤销时刻是100ns，此时也正是clk的上升沿，这个时候计数器可能进入了亚稳态，仿真出来就是不定态。
你把复位撤销时间改一下试试，比如改到105ns。
没用还是老样子