请教双时钟沿OFFSET IN约束问题
RGMII接口信号名称是: rgmii_rxc, rgmii_rx_ctrl, rgmii_rxd[3:0]。rgmii_rxc 进入FPGA后接IBUFG后输入到DCM进行phase shift,输出的125MHz时钟rx_clock用作IDDR的输入时钟端C,rgmii_rx_ctrl,rgmii_rxd[3:0]经过IBUF后接IDDR的数据输入端D。
由PCB设计原因,rgmii_rxc 没有走专用CLK输入管脚,所以rgmii_rxc 到DCM的延迟很大,相对于数据端大概有10.375ns。
UCF文件相关约束如下:
NET "rgmii_rxc" TNM_NET = rgmii_rxc;
TIMESPEC TS_ rgmii_rxc = PERIOD "rgmii_rxc" 8 ns HIGH 50%;
TIMEGRP FF_RISING = RISING rgmii_rxc;
TIMEGRP FF_FALLING = FALLING rgmii_rxc;
NET "port1_rxd*" TNM = rgmii_din;
NET "port1_rx_ctrl" TNM = rgmii_din;
TIMEGRP rgmii_din OFFSET = IN 2 VALID 4 BEFORE rgmii_rxc TIMEGRP FF_RISING;
TIMEGRP rgmii_din OFFSET = IN -2 VALID 4 BEFORE rgmii_rxc TIMEGRP FF_FALLING;
2. 问题描述:
这样约束后twr文件总报hold time出错,rgmii_rx_ctrl, rgmii_rxd[3:0]相对于rgmii_rxc的rising_edge大概都是-8.375ns的slack,貌似ISE认为时钟相对于数据的延迟10.375ns,补偿2ns后就认为还差8.375ns,但是时钟周期是8ns,这样保持时间就应该是0.375才对啊,并且好像ISE没有将DCM的输出时钟拿来进行setup/hold分析,而是直接用rgmii_rxc为时钟进行timing分析,请问应该怎么写约束才能让时序收敛. 谢谢啦!
-8.375 = 8 =-0.375,这样子还差一点啊,
把DCM输出的时钟向前相移一点就可以解决问题,要是DCM不方便,改用PLL也可。
对于offset_in分析,是以进板的时钟为基准的,因为上端芯片的输出也是以这时钟为参考告诉tco有多少,至于rx_clock,是进板时钟的派生时钟,具体时延也是可以精确分析的。 等到了下一级寄存器,就以rx_clock分析了。
谢谢eaglelsb的回复。
在DCM里已经加了-38度的phase shift,但是好象.twr里没有相应的分析。
在.twr里报的hold time错误是以DCM派生出来的时钟rx_clock为基准分析的,见下面:
#########################################################
Slack (hold path): -6.592ns (requirement - (clock path + clock arrival + uncertainty - data path))
Source: rgmii_rxd(3) (PAD)
Destination: inst_logic_top/inst_emac_top/v4_emac_block/rgmii0/rgmii_rxd_ddr_regs.3.rgmii_rxd0_iddr/FF0 (FF)
Destination Clock: inst_logic_top/rx_clock_0 rising at 0.000ns
Requirement: 3.000ns
Data Path Delay: 0.801ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Delay: 10.213ns (Levels of Logic = 2)
Clock Uncertainty: 0.180ns
Clock Uncertainty: 0.180ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.120ns
Minimum Data Path: rgmii_rxd(3) to inst_logic_top/inst_emac_top/v4_emac_block/rgmii0/rgmii_rxd_ddr_regs.3.rgmii_rxd0_iddr/FF0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C13.I Tiopi 0.786 rgmii_rxd(3)
rgmii_rxd(3)
inst_logic_top/inst_emac_top/v4_emac_block/rgmii0/rgmii_rxd_bus.3.rgmii_rxd_ibuf
ILOGIC_X2Y303.D net (fanout=1) 0.058 inst_logic_top/inst_emac_top/v4_emac_block/rgmii0/rgmii_rxd_i(3)
ILOGIC_X2Y303.CLK Tiockd (-Th) 0.043 inst_logic_top/inst_emac_top/v4_emac_block/rgmii_rxd_rising_0_i(3)
inst_logic_top/inst_emac_top/v4_emac_block/rgmii0/rgmii_rxd_ddr_regs.3.rgmii_rxd0_iddr/FF0
------------------------------------------------- ---------------------------
Total 0.801ns (0.743ns logic, 0.058ns route)
(92.8% logic, 7.2% route)
Maximum Clock Path: rgmii_rxc to inst_logic_top/inst_emac_top/v4_emac_block/rgmii0/rgmii_rxd_ddr_regs.3.rgmii_rxd0_iddr/FF0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D14.I Tiopi 0.952 rgmii_rxc
rgmii_rxc
inst_logic_top/inst_emac_top/v4_emac_block/inst_rgmii_dcm0/CLKIN_IBUFG_INST
BUFGCTRL_X0Y30.I1 net (fanout=4) 4.821 inst_logic_top/inst_emac_top/v4_emac_block/inst_rgmii_dcm0/CLKIN_IBUFG
BUFGCTRL_X0Y30.O Tbccko_O 0.900 inst_logic_top/inst_emac_top/v4_emac_block/inst_rgmii_dcm0/CLK0_BUFGMUX_VIRTEX4_INST/BUFGCTRL
inst_logic_top/inst_emac_top/v4_emac_block/inst_rgmii_dcm0/CLK0_BUFGMUX_VIRTEX4_INST/BUFGCTRL
ILOGIC_X2Y303.CLK net (fanout=65) 3.540 inst_logic_top/rx_clock_0
------------------------------------------------- ---------------------------
Total 10.213ns (1.852ns logic, 8.361ns route)
(18.1% logic, 81.9% route)
#########################################################
但是好象ISE没有考虑到时钟周期是8ns,相当于时钟沿的真正延迟是10.213-8=2.213ns,所以应该hold time应该是够的才对。
怎样才能让ISE不报hold time的ERROR呢?