综合碰到的一个error

综合碰到了一个error如下。但是error的单引号里是空的，请问我怎么去查error在哪，error是啥呢?我用的RTL compiler，这个错误是发生在最后一步synthesize -to_mapped. verilog code和tcl 附在后面了，求大神帮忙看看。谢谢。

Error   : A required object parameter could not be found. [TUI-61] [get_attribute]

        : An object named '' could not be found.

        : Check to make sure that the object exists and is of the correct type.  The 'what_is' command can be used to determine the type of an object.

Usage: get_attribute  <string> [<object>+]

    <string>:

        attribute name

    [<object>+]:

        object of interest (must be unique)

-------------verilog code------------

module test1

  (

    clk,

    rst,

    x_in,

    y_in,

    x_out

  );

input clk,rst;  

input [15:0] x_in, y_in;

output [15:0] x_out;

reg [15:0] x_out;

wire flag;

assign flag = x_in[15];

always @(posedge clk or negedge rst)

if (~rst)

x_out<='d0;

else

begin

if (flag)

x_out<=x_in+y_in;

else

x_out<=x_in-y_in;

end

endmodule

----------------------------tcl-----------------------------------------------------------------------

set_attribute lib_search_path {/users/bh/class/CPE411/STD/Synopsys}

set_attribute library {/users/bh/class/CPE411/STD/Synopsys/smic13_ff_1p32v_0c.lib}

read_hdl -v2001 {/users/bh/class/CPE411/syn1/source/test1.v}

set target_technology smic13_ff_1p32v_0c

elaborate

check_design

read_sdc -stop_on_errors /users/bh8/class/CPE411/syn1/script/timing.sdc

synthesize -to_mapped

VerlogHDL没有任何问题，你的tcl文本好像有一些问题，在写法上与我见过的不太一样，但是在这方面只是会用说不出问题所在，海涵。

read_hdl -v2001 {/users/bh/class/CPE411/syn1/source/test1.v}
读入的verdilog