寫了一個if的判斷式出現bug(已解決)

目前還是個學生在練習verilog遇到一個bug無法解決
找了很久決定來這邊求助
module addressshifter(maskin,address,a,b,c,d);
input [7:0]maskin ;
input [7:0]address;
output a,b,c,d;
reg a=0;
reg b=0;
reg c=0;
reg d=0;
reg [15:0]masknaddress;
assign masknaddress[15:0] = {maskin[7:0] , address[7:0]};
always@(maskin or address)
begin
if(masknaddress===16’b111100001XXXXXXX)  begin a=1; end
if(masknaddress===16’b111010001XXXXXXX)  begin a=1; end
if(masknaddress===16’b110110001XXXXXXX)  begin a=1; end
...
(以下都是這樣的判斷式)
end
endmodule

---------主要的bug都是這種型態的
Error (10170): Verilog HDL syntax error at addressshifter.v(20) near text ?
Error (10170): Verilog HDL syntax error at addressshifter.v(20) near text "?;  expecting ")"
Error (10170): Verilog HDL syntax error at addressshifter.v(20) near text ?

謝謝

reg类型变量不能用assign语句驱动

那要怎麼驅動呢?masknaddress也用assign驅動嗎?
assign [15:0]masknaddress;
assign masknaddress[15:0] = {maskin[7:0] , address[7:0]};
我目的是把maskin跟address合併
然後進到if裡面也可以讀到
修改後我寫成
module addressshifter(maskin,address,a,b,c,d);
input [7:0]maskin ;
input [7:0]address;
output a,b,c,d;
reg a=0;
reg b=0;
reg c=0;
reg d=0;
reg [15:0]masknaddress;
wire masknaddress[15:0] = {maskin[7:0] , address[7:0]};
always@(maskin or address)
begin
if(masknaddress===16’b111100001XXXXXXX)  begin a=1; end
if(masknaddress===16’b111010001XXXXXXX)  begin a=1; end
if(masknaddress===16’b110110001XXXXXXX)  begin a=1; end

我改成用wire驅動 錯誤仍然一樣

这样写
wire [15:0]masknaddress;
assign masknaddress[15:0] = {maskin[7:0] , address[7:0]};