请教各位关于Quartus中的Critical Warning
这种问题是不是不用管它，有谁碰见过?
你是否是用全局时钟引脚做时钟输入，PLL的时钟输入是什么引脚。
关注中 ！111
henhaohenhao
你把其他的信号接到专用的全局时钟引脚上了，如果你全局时钟的引脚够用，不需要再用这个了，那是没什么大问题的，否则全局时钟没有引到这个脚就不能用这个脚边上的PLL了
正在学习，顶一下
遇到过一样的问题，学习中
什么情况。还是没有搞清楚呀
You may see this critical warning in Quartus® II software when you drive a PLL from a clock source that is not the dedicated pin to that PLL. PLLs are designed to compensate for a particular input to output timing relationship depending on the compensation mode selected in your design. When a PLL is fed by a global clock path instead of its dedicated path, the timing relationship on the compensated path is not guaranteed.
This critical warning is triggered by mistake for Quartus II versions 6.1 through 7.2 SP1 for PLLs operating in "no compensation" mode. By definition, a PLL in "no compensation" mode does not have a defined timing relationship between the input clock to output clock destination. This critical warning will be removed in a future version of Quartus II for PLLs operating in "no compensation" mode.
解决方法
When using a non-dedicated input clock path to the PLL, and if a specific compensation is desired, you should follow these steps to produce the desired TCO (clock to out) timing relationship from the PLL input clock to the output clock destination:
1) Compile your design and perform timing analysis to determine the TCO relationship of your input to output clock path.
2) Adjust the phase of the PLL clock output to compensate for the TCO delay you determined from your timing analysis.
3) Re-compile your design and verify the desired timing for the PLL output clock.
--------------------------------------------------------------------------------