Verilog LE RAM 问题？
时间：10-02
整理：3721RD
点击：
如果clk上延后, wen 与 ren 都为 1 时,d是否等于q?
always@(posedge clk) begin
if (wen)
data[addr] <= d;
end
always@(posedge clk) begin
if (ren)
q <= data[addr];
else
q <= 8'b0;
end
always@(posedge clk) begin
if (wen)
data[addr] <= d;
end
always@(posedge clk) begin
if (ren)
q <= data[addr];
else
q <= 8'b0;
end