请教，为什么DC综合后的时序报告会有这么多的warning，应该怎么改脚本，谢谢

请教，为什么DC综合后的时序报告会有这么多的warning，都是以下面这种形式的
Warning: In design '。', net '。' driven by pin '。' has no loads. (LINT-2)
是不是我的约束不合理，我design的所有输出都设的下面这种形式
set_load 0.4 [get_ports D_out]      -pin_load
是不是不太合理，应该怎么改脚本，谢谢大虾们
（上千行的下面这种warning）
Warning: In design 'digital_cal', net 'n131125' driven by pin 'digital1_mult6_clk_r_REG522_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131111' driven by pin 'digital1_mult5_clk_r_REG29_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131109' driven by pin 'digital1_mult5_clk_r_REG1_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131093' driven by pin 'digital1_mult5_clk_r_REG27_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131092' driven by pin 'digital1_mult5_clk_r_REG26_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131091' driven by pin 'digital1_mult5_clk_r_REG25_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131090' driven by pin 'digital1_mult5_clk_r_REG24_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131089' driven by pin 'digital1_mult5_clk_r_REG23_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131087' driven by pin 'digital1_mult5_clk_r_REG21_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131085' driven by pin 'digital1_mult5_clk_r_REG19_S2/Q' has no loads. (LINT-2)
Warning: In design 'digital_cal', net 'n131084' driven by pin 'digital1_mult5_clk_r_REG18_S2/Q' has no loads. (LINT-2)

看看代码是不是这样写的，

这些warning没有问题，综合时调用的基本单元，有些管教并没有用到，就会有no load的情况。

谢谢，是我犯了个小错误 3# supergzy007

明显是内部有些CELL的管脚没用到,呵呵
如果是整个module的输出管脚无load就得注意了

严重的谢谢小编了啊！呵呵

我也学习了，最近正在学习dc。

请问小编是怎么解决问题的? 我也遇到啦

请教LZ 这个问题是怎么解决的?

明显是内部有些CELL的管脚没用到,呵呵
如果是整个module的输出管脚无load就得注意了

这个比较容易解决的吧，仔细看看DC综合出的电路图，本身很多cell的管脚就是不用的