verilog 调用Vhdl写的仿真模型
时间：10-02
整理：3721RD
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verilog中怎么调用一个VHDL的仿真model:
这个model是
entity UsbHost_model is
generic (
MaxDevice : in integer;
InputFile : in string;
OutputFile : in string
);
port (
Reset : in std_logic;
Sync : in boolean;
UsbHostSyncTime : in time;
WidthTime : in time;
HalfBasicClock : in time;
SerialClk : in std_logic;
SyncClk : in std_logic;
SelfPowered : out std_logic := '1';
SerialDataP : inout std_logic;
SerialDataN : inout std_logic
);
end UsbHost_model;
这个model是
entity UsbHost_model is
generic (
MaxDevice : in integer;
InputFile : in string;
OutputFile : in string
);
port (
Reset : in std_logic;
Sync : in boolean;
UsbHostSyncTime : in time;
WidthTime : in time;
HalfBasicClock : in time;
SerialClk : in std_logic;
SyncClk : in std_logic;
SelfPowered : out std_logic := '1';
SerialDataP : inout std_logic;
SerialDataN : inout std_logic
);
end UsbHost_model;
这个generic的infile是一个string型的变量?
这个time型的是一个时间变量?
和boolean是一个logic0或者logic1?