DCM 使用

一个开源的代码用Synplify Pro综合，然后将.edf文件在ISE中建立工程，由于使用到了DCM资源，出现了些问题，下面这是与ISE爆出问题有关的.edf文件部分内容，请各位帮忙分析解决下。

(instance (rename sd2_sdbuf "sd2.sdbuf") (viewRef PRIM (cellRef OBUF_F_12 (libraryRef VIRTEX)))

(net sdclk (joined

(portRef O (instanceRef sd2_sdbuf))

(portRef sdclk)

)

(net sdclki (joined

(portRef CLK0 (instanceRef sd0_dll1))

(portRef I (instanceRef sd2_sdbuf))

其中OBUF_F_12为代码中定义的，具体如下

component OBUF_F_12 port( O : out std_ulogic; I : in
std_ulogic ); end component;

Map不能通过，会有如下的错误：

ERRORhysDesignRules:1577 - Illegal routing. The DCM_ADV block

<clkgen0/c2.v/sd0.dll1/DCM_ADV> has CLK output pin <CLK0> with incomplete or

incorrect connectivity. Routing from the <CLK0> pin to a BUFG, BUFGCTRL or

PLL_ADV block type was not found. The DCM_ADV CLK output pins can only route

to BUFG, BUFGCTRL or PLL_ADV block types.

ERRORack:1642 - Errors in physical DRC.

如果将网表中sd2_sdbuf直接改为BUFG：

(instance
sd2_sdbuf (viewRef PRIM (cellRef BUFG (libraryRef VIRTEX)))

(net sdclk (joined

(portRef O (instanceRef sd2_sdbuf))

(portRef sdclk)

)

(net sdclki (joined

(portRef CLK0 (instanceRef sd0_dll1))

(portRef I (instanceRef sd2_sdbuf))

Map及Place & Route可以通过，但是在 Genreate Programming File会有如下的错误：

PhysDesignRules: 950-Dangling pins on block:<clkgen0/c2.v/sd0.dll1/DCM_ADV>:<DCM_ADV_DCM_ADV>. Must have a signal on one of the output clock pins.

Bitgen:25 - DRC detected 1 errors and 1 warnings. Please see the previously displayed individual error or warning messages for more details

选用的器件是Xilinx的xc5vlx110。

try it again

如果将网表中sd2_sdbuf直接改为BUFG：
源代码你有，为啥不改源码，而要改网表文件?
上面的提示说得很清楚了，因为时钟出去是要用到时钟布线资源的，PLL出去的就直接上全球时钟网络好了。