微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > 锁存器和触发器的纠结

锁存器和触发器的纠结

时间:10-02 整理:3721RD 点击:
锁存器和触发器有什么不同,它们各自在哪种环境中更加可取?
参考答案如下:A latch allows input D to flow through to the output Q when the clock isHIGH. A flip-flop allows input D to flow through to the output Q at the clockedge. A flip-flop is preferable in systems with a single clock. Latches are pref-erable in two-phase clocking systems, with two clocks. The two clocks are usedto eliminate system failure due to hold time violations. Both the phase and fre-quency of each clock can be modified independently.
         但是不是很明白,需要高手指导一下。

等待大侠解释。呵呵

电平触发和边沿触发的区别

正解!

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top