The logic for <***> does not match a known FF or Latch template.

请教：
我用Xilinx的ISE 7.1i，前仿真通过了，逻辑也正确，后仿真遇到下面这个错误。
“The logic for <***> does not match a known FF or Latch template.”
***是我程序里定义的reg型变量。
什么原因啊?
谢谢！

[原创]The logic for <***> does not match a known FF or Latch template.
上一个if忘了加else，加上就能过后仿真。

[原创]The logic for <***> does not match a known FF or Latch template.
this is a common mistake for verilog user.

thx for sharing

Thx, inspired

是因为生成了不必要的锁存器?

小编，难道就是因为if后面没有出现else所致?我加上了else，出现这个错误的变量居然反而多了一个，⊙﹏⊙b汗