DC 综合问题请教

代码很简单
module mul(a,b,c);
  input [5:0]a;
  input [5:0]b;
  output [10:0]c;
   reg  [10:0]c;
always @(posedge clk)
   begin
       if(！rst_n)
            begin
                c<=0;
            end
       else
            begin
                  c <= a*b;
           end
    end
endmodule

然后综合结果显示Warning: In design 'Lens_mul', cell 'B_2' does not drive any nets.
Warning: Module Lens_mul contains unmapped components.  The output netlist might not be read back into the system.

没有error，但是面积报告上都是0，请问是什么情况

我觉得是你敏感列表里没有rst_n的缘故，改成always @(posedge clk or negedge rst_n)试试

综合的脚本能不能贴出来?

c为什么是11位而不是12位?当然这不是根本问题，不过最好先修正了吧。

是我自己在脚本里忘记加compile了，但是综合出来还是有warning
Warning: In design 'Lens_mul_DW02_mult_0', the same net is connected to more than one pin on submodule 'FS_1'. (LINT-33)
   Net 'n3' is connected to pins 'B[3]', 'B[2]', 'B[1]'.
   Net '*Logic0*' is connected to pins 'B[0]', 'CI'.
Warning: In design 'Lens_mul_DW01_add_0', port 'A[9]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[4]' is connected directly to output port 'SUM[4]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[3]' is connected directly to output port 'SUM[3]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[2]' is connected directly to output port 'SUM[2]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[1]' is connected directly to output port 'SUM[1]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[0]' is connected directly to output port 'SUM[0]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[9]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[4]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[3]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[2]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[1]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[0]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'SUM[9]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'CO' is not connected to any nets. (LINT-28)
请问下我需要关注么

    我看了下网表 增加了一个adder 但是没有用到

2楼应该是正解

应该有两个问题：
  1.  C的位宽应该改为12位。否则乘积可能会有问题。
  2.  rst_n似乎未声明。

你是不是还有其他code没有贴出来，warning里面还有加法器，你应该整体看看问题在哪里，有些没有连的端口，为什么悬空，看影不影响你的design。

顶一下8楼
此外，乘法器就是加法器来实现的，所以出来的网表有一些悬空是正常的现象，比如有的进位位没有驱动其他单元，仔细检查网表，看看具体的原因。

在端口列表中没有申明rst_n信号， 还有你自己要清楚你是用异步复位还是同步复位， 按小编的意思估计是想用同步复位， 还有就是有个乘法器， 你要确定定义的位宽是否不溢出

帮顶了