为什么我这段代码会出错呢？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seris_gen is
    generic(n : NATURAL := 3);
    port(clk  : in  std_logic;
         reset: in  std_logic;
         q    : out std_logic;
end seris_gen;
architecture behave of seris_gen is
    signal q_n: std_logic_vector(3 downto 0);
begin
    p0: process (clk, reset) is
    variable cnt : unsigned(n-1 downto 0);
    begin
if reset = '1' then
     cnt := (others => '0');
elsif rising_edge(clk) then
     cnt := cnt + 1;
    end if
    end process p0;
    p1: process(clk, reset, cnt, q_n) is
    begin
        if (reset = '1') then
            q_n <= '1';
        elsif rising_edge(clk) then
            if (cnt[2] and cnt[1]) = '1' then
                q_n <= '0';
     else
  q_n <= '1';
            end if;
        end if;
    end process p1;
    q <= q_n;
end behave;

vhdl?

出什么错?

-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(9): Syntax error at "end seris_gen ;".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(10): Syntax error at "architecture behave of".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(14): Can't find declaration: unsigned.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(17): Bad expression.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(19): No feasible entries for infix op +.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(19): Bad expression.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(21): Syntax error at "end process p0".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(22): Can't find declaration: cnt.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(22): Can't find declaration: q_n.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(25): Can't find declaration: q_n.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(27): Syntax error at "[ 2 ]".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(27): Syntax error at "2 ] and".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(27): Syntax error at "] and cnt".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(27): Syntax error at ") = '1'".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(30): Can't find declaration: q_n.
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(32): Syntax error at "if ;".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(32): Syntax error at "if ;".
-- Error: /mnt/hgfs/home/SV_test/seris_gen.vhdl(32): Syntax error at ";".

自己太粗心大意了，port()的后面半个括号没有了，难道没有发现?错误的提示都很明显了。

语法错误，错误提示很明显啊