cadence IUS利用ISE库仿真问题？
时间：10-02
整理：3721RD
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希望大虾能帮一下忙：
这是我为了用ISE写的cadence仿真脚本
ncxlmode -R +debug +notimingcheck +access+rwc +libext+.v \
-y /eda/xilinx/ise/ISE_DS/ISE/verilog/src/simprims \
-y /eda/xilinx/ise/ISE_DS/ISE/verilog/src/unisims \
+incdir+/eda/xilinx/ise/ISE_DS/ISE/verilog/src \
./glbl.v -f allcode.f
这是错误提示
ncxlmode: 08.20-s003: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
ncxlmode: *E,NOSTUP: A problem was detected in the setup for simulation. Simulation can be done only after successfully completing design file parsing and elaboration. Also check the command line for any unintentional errors, like omission of the -name or the -nclibdirname option, if it was used for parsing, earlier.
./run.bat: line 2: -y: command not found
./run.bat: line 5: ./glbl.v: Permission denied
希望能帮一下忙，谢谢！
这是我为了用ISE写的cadence仿真脚本
ncxlmode -R +debug +notimingcheck +access+rwc +libext+.v \
-y /eda/xilinx/ise/ISE_DS/ISE/verilog/src/simprims \
-y /eda/xilinx/ise/ISE_DS/ISE/verilog/src/unisims \
+incdir+/eda/xilinx/ise/ISE_DS/ISE/verilog/src \
./glbl.v -f allcode.f
这是错误提示
ncxlmode: 08.20-s003: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
ncxlmode: *E,NOSTUP: A problem was detected in the setup for simulation. Simulation can be done only after successfully completing design file parsing and elaboration. Also check the command line for any unintentional errors, like omission of the -name or the -nclibdirname option, if it was used for parsing, earlier.
./run.bat: line 2: -y: command not found
./run.bat: line 5: ./glbl.v: Permission denied
希望能帮一下忙，谢谢！
good sharing
注意看看错误，应该是没有编译整个工程，要指定顶层文件的！
good sharing