门控时钟的上升沿和下降沿

    综合时，选取门控单元，自动插入门控时钟。库里有集成的基于上升沿触发和下降沿触发的门控时钟单元，在综合的时候是怎么选择的呢?我看到产生的网表中为clknqd1bwp7t，是基于什么选择的呢?谢谢各位前辈指教！

set_clock_gating_style命令-positive_edge_logic选项
Because the clock-gating circuitry for positive-edge triggered flip-flops differs
from that for negative-edge triggered flip-flops, you have two options for
specifying the clock gating circuitries: -positive_edge_logic (for flip-flops
inferred by a positive edge construct in the HDL code) and -negative_edge_logic (for
flip-flops inferred by a negative edge construct in the HDL code).