求助VHDL交通灯程序的多时钟错误，该怎么改啊

时间：10-02 整理：3721RD 点击：

其中一个process如下，可不可以这样计数呀，就是不同的状态要延续不同的时间

process(clk,reset,call)
begin
if(reset='1')then
cur_st<=s0;
else
if(cur_st=s0)then
if(clk'event and clk='1')then
if(call='0')then
if(count0=4999)then
cur_st<=next_st;
count0<=0;
else
count0<=count0+1;
end if;
end if;
end if;
elsif(cur_st=s1 or cur_st=s3)then
if(clk'event and clk='1')then
if(call='0')then
if(count1=24999)then
cur_st<=next_st;
count1<=0;
else
count1<=count1+1;
end if;
end if;
end if;
elsif(cur_st=s2 or cur_st=s4)then
if(clk'event and clk='1')then
if(call='0')then
if(count2=9999)then
cur_st<=next_st;
count2<=0;
else
count2<=count2+1;
end if;
end if;
end if;
end if;
end if;
end process;

复制代码

出现如下编译错误，求救啊！怎么改呀?
Error (10821): HDL error at jiaotongdeng.vhd(21): can't infer register for "cur_st.s4" because its behavior does not match any supported register model
Error (10821): HDL error at jiaotongdeng.vhd(21): can't infer register for "cur_st.s3" because its behavior does not match any supported register model
Error (10821): HDL error at jiaotongdeng.vhd(21): can't infer register for "cur_st.s2" because its behavior does not match any supported register model
Error (10821): HDL error at jiaotongdeng.vhd(21): can't infer register for "cur_st.s1" because its behavior does not match any supported register model
Error (10821): HDL error at jiaotongdeng.vhd(21): can't infer register for "cur_st.s0" because its behavior does not match any supported register model
Error (10822): HDL error at jiaotongdeng.vhd(33): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at jiaotongdeng.vhd(44): couldn't implement registers for assignments on this clock edge
Info (10018): Can't recognize finite state machine "cur_st" because it has a complex reset state
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 8 errors, 6 warnings
Error: Peak virtual memory: 214 megabytes
Error: Processing ended: Wed Aug 24 15:50:17 2011
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 10 errors, 6 warnings

你弄个附件吧，这样不好看

FF的写法有固定格式：
if reset='0' then
...
elsif(clk'event and clk='1')then
...

主要是小编对状态机的设计理解得不够，才会出现这种问题，把状态转移和状态判断的处理弄错了。

process(clk,reset,call)
      begin
            if(reset='1') then
                     cur_st<=s0;
            elsif clk'event and clk='1' then
                     if(cur_st=s0)then
--                               if(clk'event and clk='1')then
                                    if(call='0')then
                                             if(count0=4999)then
                                                      cur_st<=next_st;
                                                      count0<=0;
                                             else
                                                      count0<=count0+1;
                                             end if;
                                    end if;
                              end if;
                     elsif(cur_st=s1 or cur_st=s3)then
--                               if(clk'event and clk='1')then
                                    if(call='0')then
                                             if(count1=24999)then
                                                      cur_st<=next_st;
                                                      count1<=0;
                                             else
                                                      count1<=count1+1;
                                             end if;
                                    end if;
                              end if;
                     elsif(cur_st=s2 or cur_st=s4)then
--                               if(clk'event and clk='1')then
                                    if(call='0')then
                                             if(count2=9999)then
                                                      cur_st<=next_st;
                                                      count2<=0;
                                             else
                                                      count2<=count2+1;
                                             end if;
                                    end if;
                              end if;
                     end if;
            end if;
      end process;
这样试试看吧
还有你可以在网上搜一下，看状态机的结构是怎么样的

一般时序逻辑敏感列表中不要出现组合逻辑信号，就是process(clk,reset)
最好只有这两个敏感信号，一个时钟，一个复位。一般一个进程最好执行一种操作，分为多个进程做~

话说俺没看附件，但是觉得时钟分频就没啥意思了。因为如果都在边沿的话，分频的时钟必然慢一拍。

此为正解，VHDL程序很严格，最好遵循一定的规律。

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