Altera Stratix-III上使用Megawizard产生的ALTMEMPHY在synthesis时报错

我使用Quartus-II的Megawizard产生了DDR SDRAM的PHY IP，即ALTMEMPHY，集成我的设计中后compiler没有问题，但是当synthesis时报如下错误，我都查了好久了也找不出问题所在，哪位高手有过经验的请不吝赐教，谢谢！
Error: Output port "O" of PSEUDO_DIFF_OUT primitive "ddr_phy:u_ddr_phy|ddr_phy_alt_mem_phy:ddr_phy_alt_mem_phy_inst|ddr_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_pdiff" must drive only one OBUF primitive on the I port and cannot drive anything else File: D:/fpga/mega_ip/altmemphy/ddr_phy_alt_mem_phy.v Line: 5186
Warning: PLL "ddr_phy:u_ddr_phy|ddr_phy_alt_mem_phy:ddr_phy_alt_mem_phy_inst|ddr_phy_alt_mem_phy_clk_reset:clk|ddr_phy_alt_mem_phy_pll:full_rate.pll|altpll:altpll_component|altpll_17r3:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
Error: Input port DATAIN of DDIO_IN primitive "ddr_phy:u_ddr_phy|ddr_phy_alt_mem_phy:ddr_phy_alt_mem_phy_inst|ddr_phy_alt_mem_phy_clk_reset:clk|ddio_mimic" must come from an I/O IBUF or DELAY_CHAIN primitive File: D:/fpga/mega_ip/altmemphy/ddr_phy_alt_mem_phy.v Line: 5099

没有人知道么，自己顶一下

顶起来，这个问题有点急

你查查是不是管脚分配的问题。

搞定了，谢谢楼上的。
是因为产生的ALTMEMPHY时有个tcl会配置管脚，而我设计中top层的管脚名与tcl中的命名不一致，没配上。

我也遇到同样问题，期待答案！