对于set_max_delay这个约束的一点疑问, 请大大解惑。

本来初衷是约束Reg->Reg之间的组合逻辑的delay，结果PT报告的时候用该约束的delay值取代clock cycle，结果setup是违反了， 如果让PT重回到single cycle模式报告时序呢?

是因为这个约束必setup紧

没有太明白，

如果让PT重回到single cycle模式报告时序呢?
你说的什么意思?
这个命令是一个底层的命令，会直接取代默认的时钟间setup, hold relationship；大部分的时候不需要使用；
特例的情况可以考虑使用这个命令：比如需要打两个同步寄存器来同步异步时钟域的时候，由于第一个寄存器我们知道会进入亚稳态，这个时候用set_max_delay对第一个寄存器到第二个寄存器之间的setup relationship进行过约束，给它一些时间余量来脱离亚稳态；

Remember that set_max_delay and set_output_delay work together. For example, if you do a "set_output_delay -clock ext_10ns_clk -max 3 [get_ports data_out*]" then you're saying data_out* drives an external register that is clocked by ext_10ns_clk and the external delay to get there is 3ns. There will be a setup relationship between the internal clock driving your output register and this external clock. Most likely both clocks are the same frequency, so let's say it's a 10ns setup relationship. When you apply a "set_max_delay -from [get_keepers oe_reg*] 7", you're overriding the setup relationship from the oe_reg to the external register, so instead of 10ns it is now 7ns, but the external delay is still there. So, in this example, the set_max_delay makes the setup relationship become 7ns and 3ns of that will be used externally, so the oe has to get its data out in 4ns, basically like a 4ns Tco. You should see in the report_timing a value called oExt that shows this external delay.