为什么在quartus ii中没错在modelsim中却提示：Unknown identifier std_logic_vecter
USE ieee.std_logic_1164.all;
ENTITY test IS
END test;
ARCHITECTURE test OF test IS
SIGNAL clock: STD_LOGIC :='0';
SIGNAL a,b: INTEGER RANGE 0 TO 3:=0;
SIGNAL cc: INTEGER RANGE 0 TO 1:=0;
SIGNAL aaa,bbb: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL ccb: STD_LOGIC;
COMPONENT adder IS
PORT (a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
clk,cc:IN STD_LOGIC;
s:OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
cout:OUT STD_LOGIC);
END COMPONENT;
--------------------------------------
FUNCTION conv_std_logic(SIGNAL x:INTEGER)
RETURN STD_LOGIC IS
variable result: STD_LOGIC;
BEGIN
IF (x=0) THEN
result:= '0';
ELSE
result:= '1';
END IF;
RETURN result;
END conv_std_logic;
---------------------------------------
FUNCTION conv_std_logic_vector(SIGNAL x:INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE result:STD_LOGIC_VECTER(1 downto 0);
BEGIN
IF(x=0) then
rusult :="00";
ELSIF(x=1)then
rusult :="01";
ELSIF(x=2)then
rusult :="10";
ELSe
rusult :="11";
end if;
RETURN result;
END conv_std_logic_vector;
----------------------------------
BEGIN
aaa <= conv_std_logic_vector(a);
bbb<=conv_std_logic_vector(b);
ccb<=conv_std_logic(cc);
u1: adder PORT MAP(aaa=>a,bbb=>b,ccb=>cc,s=>open,cout=>open);
clock <= NOT clock AFTER 100ns;
PROCESS (clock)
BEGIN
IF(clock'EVENT AND clock = '1') THEN
IF( a< 3) THEN a<=a+1; ELSE a<=0;END IF ;
END IF;
END PROCESS;
PROCESS (clock,a)
BEGIN
IF (clock'EVENT AND clock='1') THEN
IF (a=3) THEN
IF( b < 3) THEN b<=b+1; ELSE b<=0;END IF ;
END IF;
END IF;
END PROCESS;
PROCESS (clock,b)
BEGIN
IF(clock'EVENT AND clock = '1') THEN
IF (b=3 AND a=0) THEN
IF (cc=0) THEN cc<=cc+1;ELSE CC<=0; END IF;
END IF;
END IF;
END PROCESS;
END test;
写错了吧，应该是std_logic_vector 是不是?
哦，谢谢。找到了，vector写错了，还有result，component PORT MAP也映射错了，昨晚就是查不出，哎！
谢谢！
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
ENTITY test IS
END test;
ARCHITECTURE test OF test IS
SIGNAL clock: STD_LOGIC :='0';
SIGNAL a,b: INTEGER RANGE 0 TO 3:=0;
SIGNAL cc: INTEGER RANGE 0 TO 1:=0;
SIGNAL aaa,bbb: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL ccb: STD_LOGIC;
COMPONENT adder IS
PORT (a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
clk,cc:IN STD_LOGIC;
s:OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
cout:OUT STD_LOGIC);
END COMPONENT;
--------------------------------------
FUNCTION conv_std_logic(SIGNAL xin:INTEGER)
RETURN STD_LOGIC IS
variable result: STD_LOGIC;
BEGIN
IF (xin=0) THEN
result:= '0';
ELSE
result:= '1';
END IF;
RETURN result;
END conv_std_logic;
---------------------------------------
FUNCTION conv_std_logic_vector(SIGNAL xin:INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE result:STD_LOGIC_VECTOR(1 downto 0);
BEGIN
IF(xin=0) then
result :="00";
ELSIF(xin=1)then
result :="01";
ELSIF(xin=2)then
result :="10";
ELSe
result :="11";
end if;
RETURN result;
END conv_std_logic_vector;
----------------------------------
BEGIN
aaa <= conv_std_logic_vector(a);
bbb <=conv_std_logic_vector(b);
ccb <=conv_std_logic(cc);-----di 50 hang----
u1: adder PORT MAP(a=>aaa,b=>bbb,cc=>ccb,clk=>clock,s=>open,cout=>open);
clock <= NOT clock AFTER 100ns;
PROCESS (clock)
BEGIN
IF(clock'EVENT AND clock = '1') THEN
IF( a< 3) THEN a<=a+1; ELSE a<=0;END IF ;
END IF;
END PROCESS;
PROCESS (clock,a)
BEGIN
IF (clock'EVENT AND clock='1') THEN
IF (a=3) THEN
IF( b < 3) THEN b<=b+1; ELSE b<=0;END IF ;
END IF;
END IF;
END PROCESS;
PROCESS (clock,b)
BEGIN
IF(clock'EVENT AND clock = '1') THEN
IF (b=3 AND a=0) THEN
IF (cc=0) THEN cc<=cc+1;ELSE CC<=0; END IF;
END IF;
END IF;
END PROCESS;
END test;
但是我吧程序改为上面的一段之后，用modelsim仿真的时候，提示：
Fatal: (vsim-3709) Signal formal "xin" bounds -2147483648 to 2147483647 (null range) are not identical to actual bounds 0 to 1.
# Time: 0 ns Iteration: 0 Process: /test/line__50 File: C:/Documents and Settings/liubing/My Documents/test.vhd
# Fatal error in Architecture test at C:/Documents and Settings/liubing/My Documents/test.vhd line 50
请问是什么原因。
附上，adder的程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adder IS
PORT (a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
clk,cc:IN STD_LOGIC;
s:OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
cout:OUT STD_LOGIC);
END adder;
ARCHITECTURE add OF adder IS
SIGNAL g,p:STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL c:STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
FOR i IN g'RANGE LOOP
IF (clk'EVENT AND clk = '1') THEN
g(i)<=a(i) AND b(i);
p(i)<=a(i) XOR b(i);
END IF;
END LOOP;
END PROCESS;
--CHAN SHENG JIN WEI WEI--
PROCESS (clk,p,g)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
c(0)<=g(0) OR (p(0) AND cc);
c(1)<=g(1) OR (p(1) AND g(0)) OR ((p(1) AND p(0)) AND cc);
END IF;
END PROCESS;
cout<=c(1);
--QIU he dan yuan---
PROCESS (clk,c)
BEGIN
IF (clk'EVENT AND clk='1') THEN
s(1)<=p(1) XOR c(0);
s(0)<=p(0) XOR cc;
END IF;
END PROCESS;
END add;
应该是变量类型声明不一样吧，第50行的CC声明和函数内声明的类型不一样，检查一下吧，VHDL代码风格要求比较严格。
是一样的啊！SIGNAL cc: INTEGER RANGE 0 TO 1:=0;
FUNCTION conv_std_logic(SIGNAL xin:INTEGER)
函数的输入类型，和cc的类型一样啊。而且用modelsim编译的时候没错，只是仿真的时候运行才出错。
找到了，是函数的INTEGER类型，我在函数参数定义的地方加上一个范围就对了，不是函数参数不能指明范围吗?