有个代码看不懂，求板上各位大大帮忙

前几天在opencores上面看到一个DFP，下载了放在ise里面跑最后发现有错误。但是作者说已经跑通了。
-- Uart wrapped in a WiGGL interface  Rob Chapman  Dec 8, 03
-- Copyright Rob Chapman 1990-2005
-- this forms a serial communications interface for DFP
-- Four EIO locations are required: sci_data, sci_rf, sci_tx, sci_baud
library ieee;
use ieee.std_logic_1164.all;
use work.dfp_types.all;
use work.program.all;
entity sci is
  port( clock : in std_logic;     -- WiGGL interface
        location : in Cell;
        write : in bit;
        datai : in Cell;
        datao : out std_logic_vector(Cell'high downto 0);
        tx_sdata : out std_logic; -- serial interface
        rx_sdata : in std_logic);
end sci;
architecture behavioral of sci is
  signal tx_pdata, rx_pdata : std_logic_vector(7 downto 0);
  signal rx_full, tx_empty, load, read : std_logic;
  signal baud : std_logic_vector(2 downto 0) := "001";
  signal address : Cell_nat;
  signal datai8 : bit_vector(7 downto 0);
begin
-- instantiate a uart
uart0 : entity work.uart
  port map(
    clock, rx_sdata, tx_sdata, rx_pdata, tx_pdata, rx_full, tx_empty, load, read, baud);
-- map address and data in
  tx_pdata <= to_stdlogicvector(datai(7 downto 0));  -- connect to data in bus
  address <= morf(location);  -- for indexing
-- map outputs to datao
  process(address,rx_pdata,rx_full,tx_empty,baud)
    variable rx_pdatab : bit_vector(7 downto 0);
  begin
    case address is
      when sci_data =>
        datao <= (others => '0');
        rx_pdatab := morf(rx_pdata);
        datao(7 downto 0) <= to_stdlogicvector(rx_pdatab);
      when sci_rf =>
        datao <= (0 => rx_full, others => '0');
      when sci_te =>
        datao <= (0 => tx_empty, others => '0');
      when sci_baud =>        
    datao <= (others => '0');
        datao(2 downto 0) <= baud;
      when others =>
        datao <= (others => 'Z');
    end case;
  end process;      
-- take care of writes and read
  process(clock)
  begin
    if rising_edge(clock) then
      load <= '0';
      read <= '0';
      if write = '1' then
        if address = sci_data then
          load <= '1';
        elsif address = sci_baud then
   
          baud <= to_stdlogicvector(datai(2 downto 0));
        end if;
      else
        if address = sci_data then
          read <= '1';
        end if;
      end if;
    end if;
  end process;
end behavioral;

ERROR:HDLParsers:3312 - "D:/dfp1/dfp1/sci.vhd" Line 53. Undefined symbol 'sci_baud'.
ERROR:HDLParsers:1209 - "D:/dfp1/dfp1/sci.vhd" Line 53. sci_baud: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "D:/dfp1/dfp1/sci.vhd" Line 70. Undefined symbol 'sci_baud'.
ERROR:HDLParsers:1209 - "D:/dfp1/dfp1/sci.vhd" Line 70. sci_baud: Undefined symbol (last report in this block)
上面说那个信号没有。但是我后来仔细看了一下，case的其他语句的那些信号量也没有啊。为什么报错就报了这个变量呀?

use work.dfp_types.all;
use work.program.all;
可能是这两个包的问题，应该是作者自己的程序包，不是VHDL默认的。