VHDL问题，想不明白只好求教了
求大家帮帮忙
我想写的这个元件功能是这样的，one_yuan，two_yuan，five_yuan是可重复投币按钮，按一下表示投一次对应钱数，然后在have_pay输出一共投了多少钱，reset高电平时清零
以下是我写的
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library ieee;
use ieee.std_logic_1164.all;
entity test is
port(one_yuan,two_yuan,five_yuan,reset：in std_logic;
have_pay：out integer range 0 to 99);
end entity test;
architecture bhv of test is
begin
process(reset,one_yuan,two_yuan,five_yuan)
variable pay_tmp:integer range 0 to 99;
begin
if reset='1' then pay_tmp:=0;
elsif one_yuan'event and one_yuan='1' then pay_tmp:=pay_tmp+1;
elsif two_yuan'event and two_yuan='1' then pay_tmp:=pay_tmp+2;
elsif five_yuan'event and five_yuan='1' then pay_tmp:=pay_tmp+5;
end if;
have_pay<=pay_tmp; --如果这句去掉编译就能通过，当然，去掉了have_pay就没有值
end process;
end architecture bhv;
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按以上编译的错误信息是（错误提示很多，但好像是同一个错误导致）
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[0] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[0]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[0]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[1] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[1]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[1]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[2] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[2]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[2]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[3] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[3]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[3]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[4] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[4]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[4]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[5] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[5]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[5]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[6] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[6]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[6]" at test.vhd(12)
Error (10822): HDL error at test.vhd(13): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at test.vhd(14): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at test.vhd(15): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 18 errors, 0 warnings
Info: Allocated 155 megabytes of memory during processing
Error: Processing ended: Wed Dec 03 12:27:24 2008
Error: Elapsed time: 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 18 errors, 0 warnings
没人人出来帮帮我吗
照错误报告看，应该是寄存器多时钟驱动了
我也遇到了这样的问题啊
如果***为非全局时钟引脚，也就是普通IO,建议不要用if ***'event and *** = '1' then 来检测上升下降沿！可以引入全局时钟信号，通过对全局时钟信号的检测，来达到获取IO引脚跳变的目的。
同意这种说法。
在VHDL中one_yuan'event and one_yuan='1' 这样的描述一般使用在时钟上的。
如果你要找出one_yuan的上升沿的话就用时钟来做
在时钟进程中如果one_yuan = ‘1’ and one_yuan_p1 = '0' 那么就可以判断出一个上升沿事件。--P1为延时后的one_yuan
当然如果你的one_yuan还没有同步到你的时钟域上，你还需要用寄存器对异步的one_yuan信号打两拍来消除亚稳态的隐患。
您写的代码太难为编译器了 无语
建议用状态机写这类逻辑
建议多用时钟使能的方式,少这么写,呵呵
看看是否能用
In FPGA, we actually use a clk for input. Your code is not assign bit width and not a clock. It is very hard to synthesize.
這樣很難run喔.....改一下吧
工具的作用是减少你的工作量，你不好好对待工具，当然罢工了，学学别人的代码，学学硬件基础。
逻辑不对，每次启动进程都要重新定义一个寄存器，这样不能保证上次的值，而且启动的时候还没有值，这样无法编译的。建议改成信号求和。同时考虑下上楼的关于全局时钟的说法。
摆脱 先学好基本功 搞清楚啥是HDL 再来谈如何设计
这个VHDL很愚蠢的，不要自由地想写啥就写啥，要按规矩来，你那么写code编译器搞不懂的。
阿哦。
你用了三个clock来同时控制一个reg的计算赋值，这个工具要疯掉的
最好引入一个clock信号来分别采one/two/three_yuan，进行处理。
不难的，如果你理解了基本综合原理，就不会写这样的代码了。
加油学习吧！
。
你三个输入信号都不是时钟输入脚，你代码中把它们都当做时钟输入使用，结果是have_pay<=pay_tmp; 这句话变成了组合逻辑而不是时序逻辑，编译的时候会出错的。你可以试着把have_pay<=pay_tmp; 这句话放到PROCESS的外面。
呵呵 这个还是得用时钟变量
自己也下去看看 哈哈 明白了 再来解答
其实原因很简单的 因为在一个进程中你同时描述了多个沿操作 这是不正确的