问个分频器的疑问

这是一个4分频的代码，仿真的波形是正确的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity div is
port(clk:in std_logic;
div_clkut std_logic);
end div;
architecture bhv of div is
signal count:integer;
begin
process(clk)
begin
if(clk'event and clk='1')
then
if(count=3)then
count<=0;
else count<=count+1;
if count<2
then
div_clk<='0';
else
div_clk<='1';
end if;
end if;
end if;
end process;
end bhv;

以下是稍改的2分频
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity div is
port(clk:in std_logic;
div_clkut std_logic);
end div;
architecture bhv of div is
signal count:integer:=0;
begin
process(clk)
begin
if(clk'event and clk='1')
then
if(count=1)then
count<=0;
else count<=count+1;
if count<1
then
div_clk<='0';
else
div_clk<='1';
end if;
end if;
end if;
end process;
end bhv;
输出的div_CLK为0.
平台是quartus
求教高手是什么问题?谢谢了

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