哪个朋友帮我用ISE仿镇下,我老过不了
时间:10-02
整理:3721RD
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module clk_fenp(
clk_in,
clk_out,
switch_8bit_in
//test
//,clk_q1,clk_q2,count,count_clk
);
input clk_in;
input[7:0] switch_8bit_in;
output clk_out;
//,clk_q1,clk_q2;
reg[7:0] count_clk;
reg clk_q1,clk_q2;
//output[7:0] count,count_clk;
wire[7:0] count;
wire estop,switch_0,switch_1;
assign switch_0=switch_8bit_in==8'b00000000 ? 1'b1 : 1'b0;
assign switch_1=switch_8bit_in==8'b00000001 ? 1'b1 : 1'b0;
assign estop=switch_0 || switch_1;
assign count=switch_8bit_in[0] ? (switch_8bit_in-1)/2+1 : switch_8bit_in/2+1;
assign clk_out=switch_1 ? clk_in :
switch_8bit_in[0] ? (clk_q1 || clk_q2) : clk_q1;
always @(posedge estop or posedge clk_in)
if(estop)
begin
count_clk<=0;
clk_q1<=0;
end
else
if(count_clk<count-1)
begin
count_clk<=count_clk+1;
clk_q1<=1;
end
else
if(count_clk<switch_8bit_in-1)
begin
count_clk<=count_clk+1;
clk_q1<=0;
end
else
begin
count_clk<=0;
clk_q1<=0;
end
always @(posedge estop or negedge clk_in)
if(estop)
clk_q2<=0;
else
clk_q2<=clk_q1;
endmodule
程序如上,,,是不是仿镇过不了下到芯片中就不行?
clk_in,
clk_out,
switch_8bit_in
//test
//,clk_q1,clk_q2,count,count_clk
);
input clk_in;
input[7:0] switch_8bit_in;
output clk_out;
//,clk_q1,clk_q2;
reg[7:0] count_clk;
reg clk_q1,clk_q2;
//output[7:0] count,count_clk;
wire[7:0] count;
wire estop,switch_0,switch_1;
assign switch_0=switch_8bit_in==8'b00000000 ? 1'b1 : 1'b0;
assign switch_1=switch_8bit_in==8'b00000001 ? 1'b1 : 1'b0;
assign estop=switch_0 || switch_1;
assign count=switch_8bit_in[0] ? (switch_8bit_in-1)/2+1 : switch_8bit_in/2+1;
assign clk_out=switch_1 ? clk_in :
switch_8bit_in[0] ? (clk_q1 || clk_q2) : clk_q1;
always @(posedge estop or posedge clk_in)
if(estop)
begin
count_clk<=0;
clk_q1<=0;
end
else
if(count_clk<count-1)
begin
count_clk<=count_clk+1;
clk_q1<=1;
end
else
if(count_clk<switch_8bit_in-1)
begin
count_clk<=count_clk+1;
clk_q1<=0;
end
else
begin
count_clk<=0;
clk_q1<=0;
end
always @(posedge estop or negedge clk_in)
if(estop)
clk_q2<=0;
else
clk_q2<=clk_q1;
endmodule
程序如上,,,是不是仿镇过不了下到芯片中就不行?

管脚配置如上说是
DDDDDDDDDDDDDD
DDDDDDDDDDDDDDDDDDDD
ddddddddddddddddddddddddddddddd
仿真都没过,不用考虑下载,不过现在很多人貌似都喜欢不仿真就下载看结果……
DDDDDDDDDDDDDDDDDDDD
仿真没过都下到FPGA中?
撞大运啊!
先看仿真为什么过不了
如何整?到底
我也学习下
先仿真在下载啊
