微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > jium007 朋友我想用你的VERLOG程序,可在ISE中老出错

jium007 朋友我想用你的VERLOG程序,可在ISE中老出错

时间:10-02 整理:3721RD 点击:
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least 38 but only 36 left after allocating other resources.
Device 9536XL44VQ was disqualified.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options.

如何优化程序?

DDDDDDDDDDDDDDDDD

dddddddddddddddddd

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top