谁来救救我？计数器问题
单片机处于一个无限循环，每次循环开始时先给出start信号（往地址0xbc00写1，FPGA内地址译码后控制信号cs_bc00_n=0），clear=0,lock=0,再读取计数器输出
用示波器观察单片机操作正确，但引出的FPGA start测试脚始终输出低电平（应为高电平），clear和lock输出正确，均为负脉冲,
以下是我的源程序：
entity data_bus is
port(
rd_n :in std_logic; ---单片机读信号
wr_n :in std_logic; ---单片机写信号
cs_8000_n:in std_logic; ---内部译码器输出信号（输入为单片机地址信号）
cs_8400_n:in std_logic;
cs_8800_n:in std_logic;
cs_8c00_n:in std_logic;
cs_9000_n:in std_logic;
cs_9400_n:in std_logic;
cs_9800_n:in std_logic;
cs_9c00_n:in std_logic;
cs_a000_n:in std_logic;
cs_a400_n:in std_logic;
cs_a800_n:in std_logic;
cs_ac00_n:in std_logic;
cs_b000_n:in std_logic;
cs_b400_n:in std_logic;
cs_b800_n:in std_logic;
cs_bc00_n:in std_logic;
cs_c000_n:in std_logic;
cs_c400_n:in std_logic;
cs_c800_n:in std_logic;
cs_cc00_n:in std_logic;
cs_d000_n:in std_logic;
cs_d400_n:in std_logic;
cs_d800_n:in std_logic;
cs_dc00_n:in std_logic;
cs_e000_n:in std_logic;
cs_e400_n:in std_logic;
cs_e800_n:in std_logic;
cs_ec00_n:in std_logic;
counter_0:in std_logic_vector(15 downto 0); ---内部计数器输出
counter_startut std_logic; ---计数器使能信号
counter_lock ut std_logic; ---计数器锁存信号
counter_clr ut std_logic; ---计数器清零信号
data_io:inout std_logic_vector(7 downto 0)); ---8位数据线
end data_bus;
architecture Behavioral of data_bus is
signal cs_n:std_logic_vector(13 downto 0);
signal hin:std_logic_vector(7 downto 0);
signal lin:std_logic_vector(7 downto 0);
signal dout:std_logic;
begin
hin<=counter_0(15 downto 8);
lin<=counter_0(7 downto 0);
counter_start<=dout;
cs_n <= cs_b400_n & cs_b000_n & cs_ac00_n & cs_a800_n &cs_a400_n &
cs_a000_n & cs_9c00_n & cs_9800_n & cs_9400_n & cs_9000_n & cs_8c00_n &
cs_8800_n & cs_8400_n & cs_8000_n;
--读
Process(rd_n,counter_0,cs_n)
begin
if rd_n = '0' then
case cs_n is
when "11111111111110" =>
dout <=hin
when "11111111111101" =>
dout <=lin
when others =>
dout <= "ZZZZZZZZ";
end case;
else
dout <= "ZZZZZZZZ";
end if;
end process;
--写
PROCESS(wr_n)
begin
if falling_edge(wr_n) then
if cs_bc00_n = '0' then
dout<=din(0); --start输出
end if;
end if;
end process;
counter_lock <= cs_b800_n;
counter_clr <= cs_c000_n;
编译警告
另外编译的时候老是出现如下警告:
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.
环境变量设置不正确?不明白什么意思,对最后结果会有影响吗?
我用的芯片是XC2S15,
各位帮帮忙啊,42度啊,热死了晕死了急死了
另外若将写过程改为:
PROCESS(wr_n)
begin
if falling_edge(wr_n) then
if cs_bc00_n = '0' then
dout<='1'; --start输出
end if;
end if;
end process;
编译时则直接将wr_n信号去掉啦,也不懂
加一句
else dout<='0'; 好了,start一直输出为高！还是不懂
高手帮忙解答啊
顶级网?好像大家都只对资源共享感兴趣也：（
救人一命胜造七级浮屠啊
各位高手帮忙啊
o my god
帮不了你
仿真工作正确么?
不过在这里
PROCESS(wr_n)
begin
if falling_edge(wr_n) then
if cs_bc00_n = '0' then
dout<=din(0); --start输出
end if;
end if;
end process;
cs_bc00_n 至少应该在sensitivity list 上。
这帖子是很早以前发的吗?2006?