请教一个数字设计的问题

Suppose we have a pipeline which will process the data in 3 cycles. Sometimes the source may have no data to send out, and sometimes the sink may not be able to receive data. Define the interface signals first, and then design the internal control logic. We must keep the throughput 1 data/cycle, and if there are any possibilities the source shall always be able to send out its data.)
请高手解答一下，非常感谢，哪怕只写出接口信号也行啊。

我觉得使用fifo或双口ram就可以，具体得看你的实际系统