ModelSim仿真出现near timescal！
时间：10-02
整理：3721RD
点击：
新人一枚，仿真出现代码如下
`timescale 1ns/1ns
module led_tb();
reg clk;
//always #DELAY clk=~clk;
initial
begin
clk=0;
end
endmodule
编译后提示
vcom -work work -2002 -explicit -vopt -stats=none {H:/FPGA_PRO/FuncTest v1.0/LED/tb/led_tb.v}
Model Technology ModelSim SE-64 vcom 10.4 Compiler 2014.12 Dec 3 2014
-- Loading package STANDARD
** Error: H:/FPGA_PRO/FuncTest v1.0/LED/tb/led_tb.v(1): near "timescal":
** Error: H:/FPGA_PRO/FuncTest v1.0/LED/tb/led_tb.v(1): VHDL Compiler exiting
跪求！大神！
`timescale 1ns/1ns
module led_tb();
reg clk;
//always #DELAY clk=~clk;
initial
begin
clk=0;
end
endmodule
编译后提示
vcom -work work -2002 -explicit -vopt -stats=none {H:/FPGA_PRO/FuncTest v1.0/LED/tb/led_tb.v}
Model Technology ModelSim SE-64 vcom 10.4 Compiler 2014.12 Dec 3 2014
-- Loading package STANDARD
** Error: H:/FPGA_PRO/FuncTest v1.0/LED/tb/led_tb.v(1): near "timescal":
** Error: H:/FPGA_PRO/FuncTest v1.0/LED/tb/led_tb.v(1): VHDL Compiler exiting
跪求！大神！
DELAY是多少！
DELAY 为10的。这里面DELAY已屏蔽掉了，不用的
端口都没有映射?