FPGA中用VHDL语言写BH1750光敏模块的显示，一直无法驱动BH1750，求大神帮助

时间：10-02 整理：3721RD 点击：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity adc is
Port ( adc_out : out  STD_LOGIC_vector(15 downto 0);
         SCL : out  STD_LOGIC;
         SDA : inout  STD_LOGIC;
         clk50MHz : in  STD_LOGIC;
         adc_en : in  STD_LOGIC);
end adc;
architecture Behavioral of adc is
constant slaveaddress2 :std_logic_vector(7 downto 0) := x"47";
constant h_resolution_mode :std_logic_vector(7 downto 0) := x"10";
constant poweron : std_logic_vector(7 downto 0) := x"01";
signal delay5us : std_logic_vector(7 downto 0);
type state is (step1,step2,step3,step4,step5,step6,step7,step8,step9,step10,step11,step12,step13,step14,
step15,step16,step17,step18,step19,step20,step21,step22,step23,step24,step25,step26,step27,step28,step29,step30,
step31,step32,step33,step34,step35,step36,step37,step38,step39,step40,step42,step43,step44,step45,step46,step47);
type state_send is(a1,a2,a3,a4);
signal state2 : state_send ;
signal state1 : state;
signal counter : integer range 0 to 7;
constant slaveaddress : std_logic_vector(7 downto 0):=x"46";
signal delay180ms : std_logic_vector(23 downto 0);
type state_receive is (b1,b2,b3,b4,b5);
signal state3 :state_receive ;
signal counter2 : integer range 8 to 15;
signal temp : std_logic_vector(15 downto 0);
signal delay5ms :std_logic_vector(7 downto 0);
signal counter3 :integer range 0 to 7;

begin
process(clk50MHz,adc_en)
begin
if adc_en='1' then
if clk50MHz' event and clk50MHz='1' then
case state1 is
when step1 => ---------start-------------
SDA -----------delay-----------------
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SCL
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter = 0 then
state1
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter=0 then
state1    ---------------stop----------------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SCL
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter = 0 then
state1
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter=0 then
state1
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
if delay180ms=x"895440" then
state1 ---------start-----------------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SCL
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter=0 then
state1    ------------------receive h data------------------------
SDA
case state3 is
when b1 =>
SCL
if delay5us=x"FA" then
state3
temp(counter2)
SCL
if delay5us=x"FA" then
if counter2=8 then
state1       ----------------Ack=0------------------------------
SDA
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1             -------------receive  low data----------------
SDA
case state3 is
when b1 =>
SCL
if delay5us=x"FA" then
state3
temp(counter3)
SCL
if delay5us=x"FA" then
if counter3 = 0 then
state1    -----------------ACK=1------------------
SDA
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1          --------------stop--------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
if delay5ms=x"64" then
state1 ---------start-------------
SDA -----------delay-----------------
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SCL       ----------send slaveaddress+write signal-------
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter = 0 then
state1 -----------receive ACK--------------
SCL
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1 -------------send power on signal--------------
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter=0 then
state1 -----------receive ACK--------------
SCL
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1    ---------------stop----------------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1 -----------------start---------------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SCL    ----------------send slaveaddress+write signal-------
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter = 0 then
state1 -----------receive ACK--------------
SCL
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1 ----------send  H- resolution mode signal-------
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter=0 then
state1 -----------receive ACK--------------
SCL
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1   -------------stop--------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1 -------------delay 180 ms ----------
if delay180ms=x"895440" then
state1 ---------start-----------------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1
SCL       -----------send slaveaddress+read signal---------
case state2 is
when a1 =>
SDA
if delay5us=x"FA" then
state2
SCL
if delay5us=x"FA" then
if counter=0 then
state1 -----------receive ACK--------------
SCL
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1    ------------------receive h data------------------------
SDA
case state3 is
when b1 =>
SCL
if delay5us=x"FA" then
state3
temp(counter2)
SCL
if delay5us=x"FA" then
if counter2=8 then
state1       ----------------Ack=0------------------------------
SDA
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1             -------------receive  low data----------------
SDA
case state3 is
when b1 =>
SCL
if delay5us=x"FA" then
state3
temp(counter3)
SCL
if delay5us=x"FA" then
if counter3 = 0 then
state1    -----------------ACK=1------------------
SDA
if delay5us=x"FA" then
state1
SCL
if delay5us=x"FA" then
state1          --------------stop--------------
SDA
if delay5us=x"FA" then
state1
SDA
if delay5us=x"FA" then
state1    ---------------delay 5 ms------------
if delay5ms=x"64" then
state1<=step1;
delay5ms<=x"00";
else
delay5ms<=delay5ms+1;
end if;       --------------over-----------------
end case;
end if;
adc_out<=temp;
else
state1<=step1;
state2<=a1;
counter<=7;
delay180ms<=x"000000";
state3<=b1;
counter2<=15;
counter3<=7;
delay5ms<=x"00";
temp<=x"0000";
SDA<='1';
SCL<='1';
delay5us<=x"00";
adc_out<=X"0000";

end if;
end process;

end Behavioral;

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