写一段HDL代码实现对输入时钟三分频的功能

1. module even_division(clk,rst,count1,count2,clk_even);
   
2. input clk;
   
3. input rst;
   
4. output [3:0] count1;
   
5. output [3:0] count2;
   
6. output clk_even; //????±è 50%μ?·??μ
   
7. reg [3:0] count1,count2;
   
8. reg clkA,clkB;
   
9. reg clktet;
   
10. wire clk_even,clk_re;
    
11. parameter N = 3;
    
12. assign clk_re = ~clk;
    
13. assign clk_even = clkA | clkB;
    
14. always @(posedge clk) begin
    
15. if(！rst) begin
    
16. count1 > 1;
    
17. always @(posedge clk) begin
    
18. if(！rst) begin
    
19. clkA > 1;
    
20. always @(posedge clk_re) begin
    
21. if(！rst) begin
    
22. clkB <= 0;
    
23. end
    
24. else if(count2 < (N-1)) begin
    
25. if(count2 == NB) begin
    
26. clkB <= ~clkB;
    
27. end
    
28. end
    
29. else begin
    
30. clkB <= ~clkB;
    
31. end
    
32. end
    
33. reg [3:0] cnt10;
    
34. always @(posedge clk) begin
    
35. if(！rst) begin
    
36. cnt10 <= 0;
    
37. end
    
38. else if(cnt10==4) begin
    
39. cnt10 <= 0;
    
40. end
    
41. else begin
    
42. cnt10 <= cnt10 + 1'b1;
    
43. end
    
44. end
    
45. always @(posedge clk) begin
    
46. if(！rst) begin
    
47. clktet <= 0;
    
48. end
    
49. else if(cnt10 == 4) begin
    
50. clktet <= ~clktet;
    
51. end
    
52. end
    
53. endmodule

不错，我之前只弄了个5分频，学习了！