Freescale MC56F8257数字信号控制器开发方案

• Crystal/resonator oscillator

• Integrated power-on reset (POR) and low-voltage interrupt (LVI) and brown-out reset module

• Inter-module crossbar connection

• Up to 54 GPIOs

• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages

• Single supply: 3.0 V to 3.6 V

MC56F825x/MC56F824x主要特性:

Core

• Efficient 56800E digital signal processor (DSP) engine with modified Harvard architecture

— Three internal address buses

— Four internal data buses

• As many as 60 million instructions per second (MIPS) at 60 MHz core frequency

• 155 basic instructions in conjunction with up to 20 address modes

• 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical operation

• Single-cycle 16 × 16-bit parallel multiplier-accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Instruction set supports DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

•JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging

Operation Range

• 3.0 V to 3.6 V operation (power supplies and I/O)

• From power-on-reset: approximately 2.7 V to 3.6 V

• Ambient temperature operating range: –40 ℃ to +105 ℃

Memory

• Dual Harvard architecture that permits as many as three simultaneous accesses to program and data memory

• 48 KB (24K x 16) to 64 KB (32K x 16) on-chip flash memory with 2048 bytes (1024 x 16) page size

• 6 KB (3K x 16) to 8 KB (4K x 16) on-chip RAM with byte addressable

• EEPROM emulation capability using flash

• Support for 60 MHz program execution from both internal flash and RAM memories

• Flash security and protection that prevent unauthorized users from gaining access to the internal flash

Interrupt Controller

• Five interrupt priority levels

— Three user programmable priority levels for each interrupt source: Level 0, 1, 2

— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, and SWI3 instruction Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, and EOnCE trace buffer

— Lowest-priority software interrupt: level LP

• Nested interrupts: higher priority level interrupt request can interrupt lower priority interrupt subroutine

• Two programmable fast interrupts that can be assigned to any interrupt source

• Notification to system integration module (SIM) to restart clock out of wait and stop states

• Ability to relocate interrupt vector table

The masking of interrupt priority level is managed by the 56800E core.

Peripheral Highlights

• One Enhanced Flex Pulse Width Modulator (eFlexPWM) module

— Up to nine output channels

— 16-bit resolution for center aligned, edge aligned, and asymmetrical PWMs

— Each complementary pair can operate with its own PWM frequency based and deadtime values

– 4 Time base

– Independent top and bottom deadtime insertion

— PWM outputs can operate as complimentary pairs or independent channels

— Independent control of both edges of each PWM output

— 6-channel NanoEdge high resolution PWM

– Fractional delay