明德扬至简设计法--分享一份实现矩阵键盘的verilog代码 可直接使用
时间：02-21
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- else begin
- state_n = state_c;
- end
- end
- FIN: begin
- if(fin2col_start)begin
- state_n = COL;
- end
- else begin
- state_n = state_c;
- end
- end
- default: state_n = COL;
- endcase
- end
- assign col2row_start = state_c==COL && end_shake_cnt;
- assign row2dly_start = state_c==ROW && end_row_index;
- assign dly2fin_start = state_c==DLY && end_row_index;
- assign fin2col_start = state_c==FIN && key_col_ff1==4'hf;
- always @(posedge clk or negedge rst_n)begin
- if(rst_n==1'b0)begin
- key_row <= 4'b0;
- end
- else if(state_c==ROW)begin
- key_row <= ~(1'b1 << row_index);
- end
- else begin
- key_row <= 4'b0;
- end
- end
- always @(posedge clk or negedge rst_n)begin
- if(rst_n==1'b0)begin
- row_cnt <= 0;
- end
- else if(add_row_cnt) begin
- if(end_row_cnt)
- row_cnt <= 0;
- else
- row_cnt <= row_cnt + 1;
- end
- end
- assign add_row_cnt = state_c==ROW || state_c==DLY;
- assign end_row_cnt = add_row_cnt && row_cnt==COL_CNT-1;
- always @(posedge clk or negedge rst_n)begin
- if(rst_n==1'b0)begin
- row_index <= 0;
- end
- else if(add_row_index) begin
- if(end_row_index)
- row_index <= 0;
- else
- row_index <= row_index + 1;
- end
- end
- assign add_row_index = end_row_cnt;
- assign end_row_index = add_row_index && row_index==x-1;
- always @(*)begin
- if(state_c==ROW)
- x = 4;
- else
- x = 1;
- end
- always @(posedge clk or negedge rst_n)begin
- if(rst_n==1'b0)begin
- key_col_get <= 0;
- end
- else if(col2row_start) begin
- if(key_col_ff1==4'b1110)
- key_col_get <= 0;
- els
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