明德扬至简设计法--分享一份实现矩阵键盘的verilog代码 可直接使用
时间：02-21
来源：互联网
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- key_col_ff1 <= 4'b1111;
- end
- else begin
- key_col_ff0 <= key_col ;
- key_col_ff1 <= key_col_ff0;
- end
- end
- always @(posedge clk or negedge rst_n)begin
- if(rst_n==1'b0)begin
- shake_cnt <= 0;
- end
- else if(add_shake_cnt)begin
- if(end_shake_cnt)
- shake_cnt <= 0;
- else
- shake_cnt <= shake_cnt + 1;
- end
- else begin
- shake_cnt <= 0;
- end
- end
- assign add_shake_cnt = key_col_ff1!=4'hf && shake_flag==0;
- assign end_shake_cnt = add_shake_cnt && shake_cnt==TIME_20MS-1;
- always @(posedge clk or negedge rst_n)begin
- if(rst_n==1'b0)begin
- shake_flag <= 0;
- end
- else if(end_shake_cnt) begin
- shake_flag <= 1'b1;
- end
- else if(key_col_ff1==4'hf) begin
- shake_flag <= 1'b0;
- end
- end
- `ifdef SCAN
- always @(posedge clk or negedge rst_n)begin
- if(rst_n==1'b0)begin
- state_c <= COL;
- end
- else begin
- state_c <= state_n;
- end
- end
- always @(*)begin
- case(state_c)
- COL: begin
- if(col2row_start)begin
- state_n = ROW;
- end
- else begin
- state_n = state_c;
- end
- end
- ROW: begin
- if(row2dly_start)begin
- state_n = DLY;
- end
- else begin
- state_n = state_c;
- end
- end
- DLY : begin
- if(dly2fin_start)begin
- state_n = FIN;
- end
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