TI KeyStone II SoC详细介绍

1.66AK2E05/02特性与描述

1.1特性

ARM Cortex-A15 MPCoreCorePac Up to Four 1.4-GHz ARM Cortex-A15 Processor Cores 4MB L2 Cache Memory Shared by all Cortex-A15 Processor Cores Full Implementation of ARMv7-A Architecture Instruction Set 32KB L1 Instruction and Data Caches per Core AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC (Multicore Shared Memory Controller) for Low Latency Access to SRAM and DDR3 One TMS320C66x DSP Core Subsystem (C66x CorePacs), Each With 1.4 GHz C66x Fixed/Floating-Point DSP Core 38.4 GMacs/Core for Fixed Point @ 1.2 GHz 19.2 GFlops/Core for Floating Point @ 1.2 GHz

Memory

32K Byte L1P Per CorePac 32K Byte L1D Per CorePac 512K Byte Local L2 Per CorePac

Integrated Rake/Search Accelarator for

Chip Rate Processing for WCDMA Rel'99, HSDPA, and HSDPA+ Reed-Muller Decoding Multicore Shared Memory Controller (MSMC) 2 MB SRAM Memory Shared by DSP CorePacs and ARM CorePac Memory Protection Unit for Both SRAM and DDR3_EMIF

Multicore Navigator

8k Multi-Purpose Hardware Queues with Queue Manager One Packet-Based DMA Engine for Zero-Overhead Transfers

Network Coprocessor with

Packet Accelerator Enables Support for Transport Plane IPsec, GTP-U, SCTP, PDCP L2 User Plane PDCP (RoHC, Air Ciphering) 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second Security Accelerator Engine Enables Support for IPSec, SRTP, 3GPP and WiMAX Air Interface, and SSL/TLS Security ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5 Up To 6.4 GbpsIPSec and 3 Gbps Air Ciphering

Ethernet Subsystem

Eight SGMII Ports with Wire Rate Switching IEEE1588 v2 (with Annex D/E/F) Support 8 GbpsTotal Ingress/Egress Ethernet BW from Core Audio/Video Bridging (802.1Qav/D6.0) QOS Capability DSCP Priority Mapping

Peripherals

Two PCIe Gen2 Controllers with Support for Two Lanes per Controller Supports Up To 5 GBaud One HyperLink Supports Connections to Other KeyStone II Architecture Devices Providing Resource Scalability Supports Up To 50 GBaud 10-Gigabit Ethernet (10-GbE) Switch Subsystem Two SGMII/XFI Ports with Wire Rate Switching and MACSEC Support IEEE1588 v2 (with Annex D/E/F) Support One 72-Bit DDR3/DDR3L Interface with Speeds Up To 1600 MTPS in DDR3 Mode EMIF16 Interface Two USB 2.0/3.0 Controllers Two UART Interfaces Three I2C Interfaces 32 GPIO Pins Three SPI Interfaces One TSIP

System Resources

Three On-Chip PLLs SmartReflex Automatic Voltage Scaling Semaphore Module Thirteen 64-Bit Timers Five Enhanced Direct Memory Access (EDMA) Modules

Commercial Case Temperature:

0°C to 85°C

Extended Case Temperature:

- 40°C to 100°C

1.2 KeyStone II 结构

TI's KeyStone II Multicore Architecture provides a unified platform for integrating RISC and DSP processing cores along with both hardware/firmware based application-specific acceleration and high performance I/Os. The KeyStone II Multicore Architecture is a proven device architecture to achieve the full performance entitlement through the following major components: TeraNet, Multicore Shared Memory Controller, Multicore Navigator, and HyperLink.

TeraNet is a multipoint to multipoint non-blocking switch fabric. Its distributed arbiter provides multiple duplex communication channels in parallel between the master and slave ports without interference. The priority based arbitration mechanism ensures the delivery of the critical traffic delivery in the system.

The Multicore Shared Mem