Question about CMOS process detail ?

I have a question about the 'thickness' and 'conductivity' parameters of
N-well in standard 2-well 0.18um CMOS Logic process, thanks!

These two parameters are very critical for the performance of RF passive parameters. thanks again!

I did not understand you well !

these are very easily found in the process file of "your" fab

they are quite new, Tech support is not very mature.

Process develop group can not give me enough support in this field, anyway, who will need so detail info about Logic process.

The two parameters is say inductor
and cap n-will pick up difference mos