which I design 100Mhz to 10Mhz ?

Hi Elcielo,

You need to provide more detailed info about the phase error you want to achieve in order to get a better answer, but here is the idea. You need to build an accumulator (to serve as the phase accumulator), the range between zero and maximum value of the accumulator will represent all phase values in one cycle of the sinusoid. Then you will use the accumulator output to address a look up table with sine values. The output of the look-up table (ram) can go straight to a DAC. There are
many improvements you can implement to this basic idea:
1. Store only one quadrant of the sine period (0-pi/2 for example), 'cause the sine's value in other quadrants can be inferred by simmetry.
2. Keep more precision in the accumulator than address bits in the LUT, then you can interpolate the LUT values for the intermediate accumulator values.
etc.

As I said, for more info, you need to give more info.

Hope this helps.

100Mhz(MC100ELT20D - TTL to PECL) -> 50Mhz(MC100EL32D - div 2)
-> 50Mhz (MC100EPT21D - LVPECL to LVTTL) -> 10Mhz(ICS525-01R)

If the phase is not important, divide by 5 and then by 2 to end up with a square wave at 10 MHz. Then run it through a low pass filter or a band pass filter. The only additional outputs will be harmonics of 10 MHz which are reduced by your filter.