Is timing important for pipelined ADC?

1. Why non-overlap clk ? first i designed full system of pipelined by ideal opamp, and switches but real comparators. I use 2 V supply so i set switch threshold 1V. It OK with ideal comparator and one stage simulation, but when i use my real comparator and connect the secound stage there is something wrong with the output of the first stage. The first time i guess that may be cause Cparacitic of the comparator of the next stage so i test by simulate with C load and switch but it not the problem. Who know my problem please introduce me something.
i use simple 2.5bit switched capaciter circuit and all of the problem happen when i use non overlap clock.