Calibration structure design for on-chip RF characterization

Hi all,

I'm wondering if there is any tutorial on the subject. In particular I'm trying to charcaterize a SiGe process with target product frequency around 5GHz. Given my standard GSG PAD configuration and my embedded devices I'm trying to understand how to layout the best calibration pattern.

One issue that I have is when the signals are routed by using two different metal layers. How does the short configuration work ?

Is it really necessary to have one calibration set for each device ?

Any feedback is welcome!

Thnx,

nathan

Some questions before the answer.

- Is your device on wafer or not ?

- What do you mean with RF characterization, perhaps S parameter measurement (or noise meas, or power meas ) ?

If the device is on wafer, you need (for S parameter measurements) a TRL (Thru, Reflect, Line) calibration kit on an allumina substrate (for example). The calibration kit is the same for all the devices

Hi,

thanks for your feedback. Here some clarification:

DUTs are on wafer and I need to extract S parameteers.

I'm mainly concerned about PADS parasistic de-embedding. The internal routing may change significantly for the smallest to the largest device and I'm afraid of a significant accuracy loss if I don't layout SOT (Short Open Trhu) for every device.

What do you think ?

Thnx,

nathan

Probably your device has a brief ustrip from the GSG pads to the DUT (adduction line). WIth a TRL calibration of the VNA (with appropriate definition of the length of the line) you may de-embedd this line also (in addition to the pad). In other words you may obtain the S parameters of just the DUT (without the contribution of the pads and the brief line).

Obviously the best solution would be to have a cal kit on the same substrate as for the DUT.

Product Note 8510-8A
"Network Analysis Applying the 8510 TRL Calibration for Non-Coaxial Measurements"

See pag. 20 fig.b for a better explanation of my previous post.

Hmmm,

I saw the paper and , even if it's not for IC's, I think it clearly shows the concept.

Thnx,

nathan

sorry, what do you mean with " it's not for IC's " ?

The document shwos the TRL calibration technique for the VNA, which allow you to set the reference plane of the measurement at the real input and output of the DUT, de-embedding any access line.

Sorry, I mean, not for on wafer testing.

nathan

Oh, sure you are right.

But the principle is valid for on wafer measurement also.

bye

Product Note 8510-8A
"Network Analysis Applying the 8510 TRL Calibration for Non-Coaxial Measurements"

you can download it from here

hxxp://cp.literature.agilent.com/litweb/pdf/5091-3645E.pdf