RF CMOS LNA LAYOUT

want to layout a cascode inductive degenerated cmos LNA.
5.8GHz CMOS.

do you know how to do a dual gate layout -- connect the gate at both sides to reduce gate resistance ? this is NOT THE SAME as a dual gate MOSFET.

any papers, thesis about this ?

thanks

"A 7-GHz 1.8dB NF CMOS Low Noise Amplifier" by Ryuichi Fujimoto etc.You can get this paper by google.

yeah it is not dual gate mosfet
but be carefull , and see how is the layout of the RF transistor is modeled
some foundaries provide the models for the gate connected from one side and others coneected from both

it affect the design in high frequency significantly specially for low noise design
coz the gate resistance is a important noise source

the paper you posted is a DUAL GATE MOSFET.

i do not want a dual gate, just connect the gates twice.