Testing of LNA. Matching in output.

Several years ago, I designed an LNA in 0.18um CMOS. Since I did on-wafer measurement, I designed the output matching network on chip using MIM cap and spiral ind. The plot of k factor vs. freq showed that k is above 1 in the whole frequency range, but it has the lowest value of 8 around 3GHz. I though it should be secure but it wasn't however: it oscillates at 2.9GHz. Someone told me in this forum that the output port of an LNA is a high Q node (mainly capacitive or inductive), it is not easy to be matched using on-chip component.

My question is:
1. What should I do if I need to test my LNA on-wafer?
2. How to avoid oscillation in the case even simulation result shows it is stable?
3. If I can measure the LNA either on-wafer or on PCB, what is the best way to test the design?

Thanks

Anyone knows about that?

you said k>1 at 2.9GHz, but are S11 and S11 both lower than 0dB? Did you check the B1 factor?

Sorry, I am not quite understand what is B1 factor. I do see something like B1 C1 in articles talking about stability of LNA, but I can not find B1 factor. Can you explain. Thanks.

cmosbjt, plz refer to the Gonzalez's book , chap. 3.6 "simutaneous conjugate match : bilinear case", And appendix C.

Under bilinear case, we can derive the simutaneously matched gammain and gammaout, and B1 represent for the solution's real part of numerator. It must be positive real number, and K>1 is only a NESSASARY requirement. (K>1 + B>0 ) or (K>1 + |delta|<1) is NESSASARY and SUFFICIENT for unconditional stable requirement.
For a K<1 2-port network, it is IMPOSSIBLE to find a simutaneously conjugate matched solution. Namely, it is impossible to match both ports.