dds spurius

DDS have a lot of adventages except one but big disadventage spurius in output signal. Spurius are mainly mathematicaly related but not all. One of way to use DDS as reference inside PLL are:
-use DDS for high clock at low clock frequency. Example 120 MHz DDS use at 20MHz. Spurius energy will be decrease substantially with wide clock duration.
-Chose frequency region with low spurius content
-use dihtering technique to spread spurius ,or put output signlal to limitter
-use cleaning loop with VCO or VCXO(if it is possible to have a little change and aditional PLL loop for additional steps)
-other combinations....etc
please specify your requirements for design

GL XTASA

HELLO XTASA,my requirements is below:
1.Frequency Range:3-6G
2.Step Size:1kHz
3.Switching Speed:400uS
4.SSB Phase Noise(dBc/Hz,typical):
<-95dBc/Hz@10KHz
5.Spurious:-60dBc
6.Harmonics:-30dBc
7.Reference:10M;128M;384M(<-145dBc/Hz@10KHz)
Please give me a detailed plan.THANKS!
My E-mail :good_luck_2008@163.com
MSN:good_luck_2008@hotmail.com
How to contact you?

what mean of Spurious?
are you want to design DDS with PLL?