manchester bit synchronizer
时间：04-11
整理：3721RD
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Hi all,
I'm designing a UHF passive RFID tag (Type-B of ISO-18000-6). The date link coding from reader to tag is 40K bps Manchester NRZ. The frame contains nine 0-1s preamble preceding the delimitter field and data field. I measure the time durations of high and low signal levels using a LO to estimate the data clock period, then decode the signal by tracking the rising and falling edges.
I'm wonder if any more advantage method to do bit synchronization as well as improve SNR. It's said that Machester coding is more easy to be synchronized and a digital PLL is suitable for this task, but I can't find a detail implemention.
A difficulty is that the LO in chip can't provide a constant frequency. Because the power of the chip is aquired from the EM wave and working voltage is lower when the reader transmitt bit 0 than bit 1, the frequency of LO deviates about 30~40% at different bit level.
Thanks for any information.
I'm designing a UHF passive RFID tag (Type-B of ISO-18000-6). The date link coding from reader to tag is 40K bps Manchester NRZ. The frame contains nine 0-1s preamble preceding the delimitter field and data field. I measure the time durations of high and low signal levels using a LO to estimate the data clock period, then decode the signal by tracking the rising and falling edges.
I'm wonder if any more advantage method to do bit synchronization as well as improve SNR. It's said that Machester coding is more easy to be synchronized and a digital PLL is suitable for this task, but I can't find a detail implemention.
A difficulty is that the LO in chip can't provide a constant frequency. Because the power of the chip is aquired from the EM wave and working voltage is lower when the reader transmitt bit 0 than bit 1, the frequency of LO deviates about 30~40% at different bit level.
Thanks for any information.