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clock recovery question

时间:04-11 整理:3721RD 点击:
hi ,

i am working on a RF voice link ,

my problem is not really in the RF section till now , as it is in the clock recovery part at the receiver.

i know that i have to use a pll circuit or something to re generate the Tx clock , so i can use it synchronously at the Rx

the problem is that i havent done it before , so i was wondering , if the isea of PLL is really a practical method , or if there is another more practical and accurate method .

thank you so much
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Hi

You need to use a digital PLL type for clock extraction - digital PLL use a frequency divider insted of VCO section adjsting the frequency response by dividing the clock frequency {as in analog pll}


All the best


Bobi

Hi,
I suggest you send some pilot also so it becomes very easy. This is possible if you are designing the TX also.
brmadhukar

this is a great idea , to send a pilot with the frequency i want , and utilize it in the Rx synchronization as a clock ..

but my problem is , that the data rate (clock) is way far from the carrier .

i mean , i am modulating at the freq band of 400 Mhz (ISM band) while the data rate is only 16 Kbps !

a good idea tis to send a pilot at the frequency of (for example) 16 Mhz , and at the Rx it can be divided by 1000 to be 16 KHz !

but wouldnt that be a bit impractical ? (to send data on 400MHz and pilot at 16Mhz ?)

so a pilot frequency is a good idea , but will also require additional BPF at the i/p of the Rx .

i dont know , isnt there a simpler way for the job ?

thanks so much for ur care ..

Depends on your modulation,

You can use a PLL to lock data clock or (2 x data clock) if the line coding has a component on data clock... This is the easier way.

I hope it helps you

TaPa

i think i should experiment with a pll , and see the results

thanks

but if anybody can help me more with the implementation of pll

i know it's components , (vco , comparator , ... )

but i need help with part numbers and so

thanks again!

Hi,
What is the bandwidth of your signal? Can you accomodate the carrier within the bandwidth and use synchronous demodulation?

For your last question why don't you implement the PLL in software?

brmadhukar

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