Help need design a 500MHz to 16G reference sine clock

Hi


we want to design a way to address 500MHz to 16GHz reference clock to a PHY chip for high speed applicaiton.

it seems the VCO and PLL can not reack to such range, how to get this solution and documents need help comments if you have good way, thanks

Regards

https://www.crowdsupply.com/era-instruments/erasynth

Sometime it's better to purchase than build.

Thanks comments, we want to integrate into product, so this one good, but size is big, we want to find a solutions.

Analog devices has some monolithic PLL/VCO chips that are specced up to ~13GHz (see ADF5356, etc). You might get by using that, and switching in a frequency multiplier for the upper range.

I gave you that link to inspire from their crowd founded works.If the equipment size is big, you can obtain an inspiration from..
https://github.com/erainstruments/er...h-rev3-sch.pdf
I think it will work for your target.