I design a LNA

I design a LNA work on 3.5G, simulate it with ADS, and layout it with smic0.18. Can anybody give me some suggestion about layout.

that depends where you start for your layout work..
When I do my layout work for the first time, some design rule mistakes almost kill me.

What's your meaning about design rule mistakes? You mean that some design rule in DRC file are not good when apply to the layout of LNA? And can you give me some suggestion when layout the inductance? Thank you!

i think u should read related tech documents througly fistt