induced gate noise
As is known that the induced gate noise cannot be neglected in the high frequency designs, however, it's not uncommon that designers can only get the RF models from foundies that do not take the induced gate noise into account. If requested, the foundries may provide a look-up table containing the four noise parameters.
How to perform the simulation with the induced gate noise? Or how to use the look-up tables provided by the foundries?
Can anyone here help me out? Thank you.
Sorry, I made a little mistake. The title should be "How to Perform Noise Simulation with Induced Gate Noise?"
Thank you.
In my opinion, until now no-one can simulate this noise accurately, becasue the real correlation between gate and drain noise is still in study.
Yibin.
Yes, you're probably right. However, I guess there must be some way to perform the simulation based on the known noise theories, provided that the foundries only give designers the measured four noise parameters.
Thank you.
Check Shaeffer's thesis, "The design and implementation of low-power CMOS receivers",p.93-96. He developed a practical way to simulate gate noise. I remember that there are some resources on Lee's website, one of them are the spice file to simulate the gate noise.